ST STM32F40 Series Reference Manual page 1205

USB on-the-go high-speed (OTG_HS)
Bit 31 BSYDNE: I2C Busy/Done
The application sets this bit to 1 to start a request on the I
complete, the core deasserts this bit to 0. As long as the bit is set indicating that the I
interface is busy, the application cannot start another request on the interface.
Bit 30 RW: Read/Write Indicator
This bit indicates whether a read or write register transfer must be performed on the
interface.
0: Write
1: Read
Note: Read/write bursting is not supported for registers.
Bit 29 Reserved, must be kept at reset value.
Bit 28 I2CDATSE0: I
This bit is used to select the full-speed interface USB mode.
0: VP_VM USB mode
1: DAT_SE0 USB mode
Bits 27:26 I2CDEVADR: I
This bit selects the address of the I
corresponding to the one used by the core for OTG signalling.
Bit 25 Reserved, must be kept at reset value.
Bit 24 ACK: I
This bit indicates whether an ACK response was received from the I
BSYDNE is cleared by the core, after the application has initiated an I
0: NAK
1: ACK
Bit 23 I2CEN: I
This bit enables the I
Bits 22:16 ADDR: I
This is the 7-bit I
including the I
Bits 15:8 REGADDR: I
These bits allow to program the address of the register to be read from or written to.
Bits 7:0 RWDATA: I
After a register read operation, these bits hold the read data for the application.
During a write operation, the application can use this register to program the data to be
written to a register.
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2
C DatSe0 USB mode
2
C Device Address
2
C ACK
2
C Enable
2
C master to initiate transactions on the I
2
C Address
2
C device address used by the application to access any external I
2
C slave on a USB 1.1 OTG full-speed serial transceiver.
2
C Register Address
2
C Read/Write Data
Doc ID 018909 Rev 4
2
C interface. When the transfer is
2
C slave on the USB 1.1 full-speed serial transceiver
RM0090
2
2
C slave. It is valid when
2
C access.
2
C interface.
2
C slave,
C