ST STM32F40 Series Reference Manual page 1244

RM0090
OTG_HS device OUT endpoint 0 transfer size register (OTG_HS_DOEPTSIZ0)
Address offset: 0xB10
Reset value: 0x0000 0000
The application must modify this register before enabling endpoint 0. Once endpoint 0 is
enabled using the Endpoint enable bit in the device control endpoint 0 control registers
(EPENA bit in OTG_HS_DOEPCTL0), the core modifies this register. The application can
only read this register once the core has cleared the Endpoint enable bit.
Nonzero endpoints use the registers for endpoints 1–15.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STUPC
NT
Reserved
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:29 STUPCNT: SETUP packet count
Bits 28:20 Reserved, must be kept at reset value.
Bit 19 PKTCNT: Packet count
Bits 18:7 Reserved, must be kept at reset value.
Bits 6:0 XFRSIZ: Transfer size
rw
This field specifies the number of back-to-back SETUP data packets the endpoint can
receive.
01: 1 packet
10: 2 packets
11: 3 packets
This field is decremented to zero after a packet is written into the RxFIFO.
Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only
after it has exhausted the transfer size amount of data. The transfer size can be set to the
maximum packet size of the endpoint, to be interrupted at the end of each packet.
The core decrements this field every time a packet is read from the RxFIFO and written to
the external memory.
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
9 8 7
Reserved
6 5 4 3 2 1 0
XFRSIZ
rw rw rw rw rw rw rw
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