ST STM32F40 Series Reference Manual page 1206

RM0090
OTG_HS general core configuration register (OTG_HS_GCCFG)
Address offset: 0x038
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 NOVBUSSENS: V
When this bit is set, V
option removes the need for a dedicated V
other purposes such as a shared functionality. V
another general purpose input pad and monitored by software.
This option is only suitable for host-only or device-only applications.
0: V
1: V
Bit 20 SOFOUTEN: SOF output enable
0: SOF pulse not available on PAD
1: SOF pulse available on PAD
Bit 19 VBUSBSEN: Enable the V
0: V
1: V
Bit 18 VBUSASEN: Enable the V
0: V
1: V
Bit 17 I2CPADEN: Enable I
0: I
1: I
Bit 16 PWRDWN: Power down
Used to activate the transceiver in transmission/reception
0: Power down active
1: Power down deactivated ("Transceiver active")
Bits 15:0 Reserved, must be kept at reset value.
rw rw rw rw rw rw
sensing disable option
BUS
is considered internally to be always at V
BUS
sensing available by hardware
BUS
sensing not available by hardware.
BUS
BUS
sensing "B" disabled
BUS
sensing "B" enabled
BUS
BUS
sensing "A" disabled
BUS
sensing "A" enabled
BUS
2
C bus connection for the external I
2
C bus disabled
2
C bus enabled
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
pad, and leave this pad free to be used for
BUS
connection can be remapped on
BUS
sensing "B" device
sensing "A" device
9 8 7 6 5 4
Reserved
valid level (5 V). This
BUS
2
C PHY interface.
3 2 1 0
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