ST STM32F40 Series Reference Manual page 1228

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RM0090
OTG_HS device V
Address offset: 0x0828
Reset value:
This register specifies the V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 VBUSDT: Device V
OTG_HS device V
Address offset: 0x082C
Reset value: 0x0000 05B8
This register specifies the V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DVBUSP: Device V
discharge time register (OTG_HS_DVBUSDIS)
BUS
0x0000 17D7
BUS
Reserved
discharge time
BUS
Specifies the V
discharge time after V
BUS
V
discharge time in PHY clocks / 1 024
BUS
Depending on your V
BUS
pulsing time register (OTG_HS_DVBUSPULSE)
BUS
BUS
Reserved
pulsing time
BUS
Specifies the V
pulsing time during SRP. This value equals:
BUS
V
pulsing time in PHY clocks / 1 024
BUS
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
discharge time after V
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
pulsing during SRP. This value equals:
BUS
load, this value may need adjusting.
pulsing time during SRP.
pulsing during SRP.
BUS
9
8
7
6
5
VBUSDT
9
8
7
6
5
DVBUSP
rw rw rw rw rw rw rw rw rw rw rw rw
4
3
2
1
0
4
3
2
1
0
1228/1422

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