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RM0090
OTG_HS device IN endpoint FIFO empty interrupt mask register:
(OTG_HS_DIEPEMPMSK)
Address offset: 0x834
Reset value: 0x0000 0000
This register is used to control the IN endpoint FIFO empty interrupt generation
(TXFE_OTG_HS_DIEPINTx).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits
These bits act as mask bits for OTG_HS_DIEPINTx.
TXFE interrupt one bit per IN endpoint:
Bit 0 for IN endpoint 0, bit 15 for IN endpoint 15
0: Masked interrupt
1: Unmasked interrupt
OTG_HS device each endpoint interrupt register (OTG_HS_DEACHINT)
Address offset: 0x0838
Reset value: 0x0000 0000
There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 OEP1INT: OUT endpoint 1 interrupt bit
Bits 16:2 Reserved, must be kept at reset value.
Bit 1 IEP1INT: IN endpoint 1interrupt bit
Bit 0
Reserved
Reserved, must be kept at reset value.
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
9
INEPTXFEM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
9
Reserved
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1230/1422
1
0
1
0
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