ST STM32F40 Series Reference Manual page 1166

RM0090
(OTG_HS_DIEPINTx/)OTG_HS_DOEPINT0) registers. The bits available inside the
control and transfer size registers slightly differ from other endpoints.
●
5 IN endpoints
–
–
–
–
●
5 OUT endpoints
–
–
–
–
Endpoint controls
The following endpoint controls are available through the device endpoint-x IN/OUT control
register (DIEPCTLx/DOEPCTLx):
●
Endpoint enable/disable
●
Endpoint activation in current configuration
●
Program the USB transfer type (isochronous, bulk, interrupt)
●
Program the supported packet size
●
Program the Tx-FIFO number associated with the IN endpoint
●
Program the expected or transmitted data0/data1 PID (bulk/interrupt only)
●
Program the even/odd frame during which the transaction is received or transmitted
(isochronous only)
●
Optionally program the NAK bit to always send a negative acknowledge to the host
regardless of the FIFO status
● Optionally program the STALL bit to always stall host tokens to that endpoint
●
Optionally program the Snoop mode for OUT endpoint where the received data CRC is
not checked
They can be configured to support the isochronous, bulk or interrupt transfer type.
They feature dedicated control (OTG_HS_DIEPCTLx), transfer configuration
(OTG_HS_DIEPTSIZx), and status-interrupt (OTG_HS_DIEPINTx) registers.
The Device IN endpoints common interrupt mask register (OTG_HS_DIEPMSK)
allows to enable/disable a single endpoint interrupt source on all of the
IN endpoints (EP0 included).
They support incomplete isochronous IN transfer interrupt (IISOIXFR bit in
OTG_HS_GINTSTS). This interrupt is asserted when there is at least one
isochronous IN endpoint for which the transfer is not completed in the current
frame. This interrupt is asserted along with the end of periodic frame interrupt
(OTG_HS_GINTSTS/EOPF).
They can be configured to support the isochronous, bulk or interrupt transfer type.
They feature dedicated control (OTG_HS_DOEPCTLx), transfer configuration
(OTG_HS_DOEPTSIZx) and status-interrupt (OTG_HS_DOEPINTx) registers.
The Device Out endpoints common interrupt mask register
(OTG_HS_DOEPMSK) allows to enable/disable a single endpoint interrupt source
on all OUT endpoints (EP0 included).
They support incomplete isochronous OUT transfer interrupt (INCOMPISOOUT
bit in OTG_HS_GINTSTS). This interrupt is asserted when there is at least one
isochronous OUT endpoint on which the transfer is not completed in the current
frame. This interrupt is asserted along with the end of periodic frame interrupt
(OTG_HS_GINTSTS/EOPF).
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
1166/1422