Table of Contents
Advertisement
USB on-the-go high-speed (OTG_HS)
OTG_HS Host all channels interrupt register (OTG_HS_HAINT)
Address offset: 0x414
Reset value: 0x0000 000
When a significant event occurs on a channel, the host all channels interrupt register
interrupts the application using the host channels interrupt bit of the Core interrupt register
(HCINT bit in OTG_HS_GINTSTS). This is shown in
per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the
application sets and clears bits in the corresponding host channel-x interrupt register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 HAINT: Channel interrupts
One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
OTG_HS host all channels interrupt mask register (OTG_HS_HAINTMSK)
Address offset: 0x418
Reset value: 0x0000 0000
The host all channel interrupt mask register works with the host all channel interrupt register
to interrupt the application when an event occurs on a channel. There is one interrupt mask
bit per channel, up to a maximum of 16 bits.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 HAINTM: Channel interrupt mask
0: Masked interrupt
1: Unmasked interrupt
One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
1211/1422
Reserved
Reserved
Doc ID 018909 Rev 4
Figure
383. There is one interrupt bit
9
r
r
r
r
r
r
r
9
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RM0090
8
7
6
5
4
3
2
HAINT
r
r
r
r
r
r
r
8
7
6
5
4
3
2
HAINTM
1
0
r
r
1
0
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32F40 Series and is the answer not in the manual?
Questions and answers