ST STM32F40 Series Reference Manual page 1224

RM0090
OTG_HS device status register (OTG_HS_DSTS)
Address offset: 0x808
Reset value: 0x0000 0010
This register indicates the status of the core with respect to USB-related events. It must be
read on interrupts from the device all interrupts (OTG_HS_DAINT) register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:8 FNSOF: Frame number of the received SOF
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 EERR: Erratic error
The core sets this bit to report any erratic errors.
Due to erratic errors, the OTG_HS controller goes into Suspended state and an interrupt is
generated to the application with Early suspend bit of the Core interrupt register (ESUSP bit
in OTG_HS_GINTSTS). If the early suspend is asserted due to an erratic error, the
application can only perform a soft disconnect recover.
Bits 2:1 ENUMSPD: Enumerated speed
Indicates the speed at which the OTG_HS controller has come up after speed detection
through a chirp sequence.
00: High speed
01: Reserved
10: Reserved
11: Full speed (PHY clock is running at 48 MHz)
Others: reserved
Bit 0 SUSPSTS: Suspend status
In peripheral mode, this bit is set as long as a Suspend condition is detected on the USB.
The core enters the Suspended state when there is no activity on the USB data lines for a
period of 3 ms. The core comes out of the suspend:
– When there is an activity on the USB data lines
– When the application writes to the Remote wakeup signaling bit in the Device control register
(RWUSIG bit in OTG_HS_DCTL).
FNSOF
r r r r r r r
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
9 8
r r r r r r r
7 6 5 4 3 2 1
Reserved
r r r
1224/1422
0
r