ST STM32F40 Series Reference Manual page 1202

RM0090
Peripheral mode:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:25 Reserved, must be kept at reset value.
Bits 24:21 FRMNUM: Frame number
Bits 20:17 PKTSTS: Packet status
Bits 16:15 DPID: Data PID
Bits 14:4 BCNT: Byte count
Bits 3:0 EPNUM: Endpoint number
OTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ)
Address offset: 0x024
Reset value: 0x0000 0200
The application can program the RAM size that must be allocated to the RxFIFO.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 RXFD: RxFIFO depth
FRMNUM PKTSTS
r r
This is the least significant 4 bits of the frame number in which the packet is received on the
USB. This field is supported only when isochronous OUT endpoints are supported.
Indicates the status of the received packet
0001: Global OUT NAK (triggers an interrupt)
0010: OUT data packet received
0011: OUT transfer completed (triggers an interrupt)
0100: SETUP transaction completed (triggers an interrupt)
0110: SETUP data packet received
Others: Reserved
Indicates the Data PID of the received OUT data packet
00: DATA0
10: DATA1
01: DATA2
11: MDATA
Indicates the byte count of the received data packet.
Indicates the endpoint number to which the current received packet belongs.
Reserved
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 1024
The power-on reset value of this register is specified as the largest Rx data FIFO depth.
Doc ID 018909 Rev 4
USB on-the-go high-speed (OTG_HS)
DPID BCNT
r
9 8 7 6 5 4 3
r
9 8 7 6 5 4 3
RXFD
r/rw
2 1 0
EPNUM
r
2 1 0
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