ST STM32F40 Series Reference Manual page 1245

USB on-the-go high-speed (OTG_HS)
OTG_HS device endpoint-x transfer size register (OTG_HS_DIEPTSIZx)
(x = 1..3, where x = Endpoint_number)
Address offset: 0x910 + (Endpoint_number × 0x20)
Reset value: 0x0000 0000
The application must modify this register before enabling the endpoint. Once the endpoint is
enabled using the Endpoint enable bit in the device endpoint-x control registers (EPENA bit
in OTG_HS_DIEPCTLx), the core modifies this register. The application can only read this
register once the core has cleared the Endpoint enable bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MCNT
rw/ rw/
r/r r/r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
w w
Bit 31 Reserved, must be kept at reset value.
Bits 30:29 MCNT: Multi count
Bit 28:19 PKTCNT: Packet count
Bits 18:0 XFRSIZ: Transfer size
1245/1422
PKTCNT
For periodic IN endpoints, this field indicates the number of packets that must be transmitted
per frame on the USB. The core uses this field to calculate the data PID for isochronous IN
endpoints.
01: 1 packet
10: 2 packets
11: 3 packets
Indicates the total number of USB packets that constitute the Transfer Size amount of data
for this endpoint.
This field is decremented every time a packet (maximum size or short packet) is read from
the TxFIFO.
This field contains the transfer size in bytes for the current endpoint. The core only interrupts
the application after it has exhausted the transfer size amount of data. The transfer size can
be set to the maximum packet size of the endpoint, to be interrupted at the end of each
packet.
The core decrements this field every time a packet from the external memory is written to the
TxFIFO.
Doc ID 018909 Rev 4
9 8 7 6 5 4
XFRSIZ
RM0090
3 2 1 0