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PLL Block
EXTAL
Predivider
1 to 31
PD[4–0]
5.3.1
Frequency Predivider
Clock input frequency division is accomplished by means of a frequency predivider of the input frequency. The pre-divider ranges from 1 to
31. The pre-divider must never be set to zero. The output frequency of the pre-divider (Fref) must be between 5 MHz and 20 MHz to guarantee
proper operation.
5.3.2
Phase Detector and Charge Pump Loop Filter
The Phase Detector detects any phase difference between the external clock (
the point where there is negligible phase difference and the frequency of the two inputs is identical, the PLL is in the locked state. The charge
pump loop filter receives signals from the Phase Detector and either increases or decreases the voltage applied to the VCO based on the Phase
Detector signals.
5.3.3
Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) can oscillate at frequencies from 300 MHz to 600 MHz. The VCO output frequency is determined
by the voltage applied to it by the charge pump that corresponds to the PLL input frequency (Fref). The VCO frequency is a function of the
input frequency as well as the multiplication components (Multiplication factor (MF) and Feedback Multiplier (FM)).
5.3.4
PLL DividerS
As part of the PLL output stage, there are two divide modules (each is a divide by 2 module) controlled by the OD0 and OD1 bits in the PCTL
register. These two bits control the PLL feedback multiplier (FM) as well as the output divide factor (OD). The feedback multiplier is a
frequency divider implemented in the PLL feedback loop thus operating as a PLL multiplier and can be programmed to multiply the VCO
output frequency up by a factor of 2 or 4. See
one divide module is in the feedback loop (OD1=0) FM = 2. When two divide modules are in the feedback loop (OD1=1) FM = 4. Note that
when OD1 is changed, the PLL will lose lock.
The output divide factor (OD) determines the PLL output frequency as a function of the VCO frequency. The PLL output frequency can be
programmed to be the VCO frequency divided by 2 or 4. The output divide factor (OD) is determined by both the OD1 and OD0 bits. See
Table
5-2. Note that the PLL will not lose lock when OD0 is changed since OD0 is not in the PLL loop. The PLL will lose lock, however,
when OD1 is changed. Also, note that the output divide factor (OD) should not be programmed such that both OD0 = 0 and OD1 = 0.
5-2
Fref
Phase
Charge Pump
Detector
and
Loop Filter
Frequency
Divider
MF[7–0]
1 to 255
Figure 5-2. PLL Block Diagram
Table
5-1. The number of divide modules in the PLL loop is determined by the OD1 bit. When
Table 5-1. Feedback Multiplier (FM); FM = 2(1 + OD1)
OD1
0
1
DSP56374 Users Guide, Rev. 1.2
OD1
VCO Out
0
VCO
1
Divide
by 2
FM
Divide
by 2
0
1
OD0
NOTE:
5 MHz < Fref < 20 MHz
300 MHz < VCO Out< 600 MHz
EXTAL
) and the phase of the clock generated by the PLL. At
FM
2
4
Clock
0
Generator
PLL Out
1
PEN
Freescale Semiconductor
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