Xilinx Zynq-7000 User Manual page 91

User FPGA Logic
The user FPGA logic block shown in
connected to an external DDR2 or DDR3 SDRAM. The user FPGA logic connects to the
Memory Controller through the user interface. An example user FPGA logic is provided with
the core.
AXI4 Slave Interface Block
The AXI4 slave interface maps AXI4 transactions to the UI to provide an industry-standard
bus protocol interface to the Memory Controller.
User Interface Block and User Interface
The UI block presents the UI to the user FPGA logic block. It provides a simple alternative to
the native interface by presenting a flat address space and buffering read and write data.
Memory Controller and Native Interface
The front end of the Memory Controller (MC) presents the native interface to the UI block.
The native interface allows the user design to submit memory read and write requests and
provides the mechanism to move data from the user design to the external memory device,
and vice versa. The backend of the Memory Controller connects to the physical interface
and handles all the interface requirements to that module. The Memory Controller also
provides a reordering option that reorders received requests to optimize data throughput
and latency.
PHY and the Physical Interface
The front end of the PHY connects to the Memory Controller. The backend of the PHY
connects to the external memory device. The PHY handles all memory device signal
sequencing and timing.
IDELAYCTRL
An IDELAYCTRL is required in any bank that uses IDELAYs. IDELAYs are associated with the
data group (DQ). Any bank/clock region that uses these signals require an IDELAYCTRL.
The MIG tool instantiates one IDELAYCTRL and then uses the IODELAY_GROUP attribute
(see the iodelay_ctrl.v module). Based on this attribute, the Vivado Design Suite
properly replicates IDELAYCTRLs as needed within the design.
The IDELAYCTRL reference frequency is set by the MIG tool to either 200 MHz, 300 MHz, or
400 MHz depending on memory interface frequency and speed grade of the FPGA. Based
on the IODELAY_GROUP attribute that is set, the Vivado Design Suite replicates the
IDELAYCTRLs for each region where the IDELAY blocks exist.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Figure 1-51 is any FPGA design that requires to be
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