Xilinx Zynq-7000 User Manual page 588

Memory Controller
In the core default configuration, the Memory Controller (MC) resides between the UI block
and the physical layer. This is depicted in
X-Ref Target - Figure 4-46
The Memory Controller is the primary logic block of the memory interface. It receives
requests from the UI and stores them in a logical queue. Requests are optionally reordered
to optimize system throughput and latency.
The Memory Controller block is organized as four main pieces:
• Configurable number of "bank machines"
• Configurable number of "rank machines"
• Column machine
• Arbitration block
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Figure
Figure 4-46: Memory Controller
www.xilinx.com
4-46.
Send Feedback
588