Xilinx Zynq-7000 User Manual page 218

Table 1-70: 32-Bit DDR3 Interface Contained in Two Banks (Cont'd)
Bank Signal Name
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Table 1-71 shows an example of a 64-bit DDR3 interface contained within three banks. This
example uses four 2 Gb x16 components.
Table 1-71: 64-Bit DDR3 Interface in Three Banks
Bank Signal Name
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Byte Group
– B_00
DQ7 A_11
DQ6 A_10
DQ5 A_09
DQ4 A_08
DQS0_P A_07
DQS0_N A_06
DQ3 A_05
DQ2 A_04
DQ1 A_03
DQ0 A_02
DM0 A_01
RESET_N A_00
VRN –
Byte Group
VRP –
DQ63 D_11
DQ62 D_10
DQ61 D_09
DQ60 D_08
DQS7_P D_07
DQS7_N D_06
DQ59 D_05
DQ58 D_04
DQ57 D_03
DQ56 D_02
DM7 D_01
– D_00
DQ55 C_11
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I/O Type I/O Number
N 13
P 12
N 11
P 10
N 9
P 8
N 7
P 6
N 5
P 4
N 3
P 2
N 1
SE 0
I/O Type I/O Number
SE 49
P 48
N 47
P 46
N 45
P 44
N 43
P 42
N 41
P 40
N 39
P 38
N 37
P 36
Special
Designation
–
–
–
–
–
DQS-P
DQS-N
–
–
–
–
–
–
–
Special
Designation
–
–
–
–
–
DQS-P
DQS-N
–
–
–
–
–
–
–
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