Xilinx Zynq-7000 User Manual page 613

Figure 4-56 and
parameter MEM_ADDR_ORDER. This parameter can take the following values:
• BANK_ROW_COLUMN – Address map is as shown in
• ROW_BANK_COLUMN – Address map is as shown in
• TG_TEST – Address map is used for testing purpose only. It enables the address remap
to test address access to different portions of the DRAM. It remaps the address as
explained in the following examples. The remap is done within the UI portion of the
controller.
The row width, column width, and bank width value settings are assumed for the following
Note:
examples:
Row Width – 15
°
Bank Width – 3
°
Column Width – 10
°
Example (1) – When the selected option in the MIG GUI is BANK_ROW_COLUMN and the
address to the controller is mapped accordingly.
BANK
Address
Bits
27 26 25 24 23 22
B2 B1 B0 R14 R13 R12 R11 R10 R9
BANK
Address
Bits
27 26 25 24 23 22
R0 C9 C8 R4 R3 B2
Example (2) – When the selected option in the MIG GUI is ROW_BANK_COLUMN and the
address to the controller is mapped accordingly.
ROW Address Bits
27 26 25 24 23 22
R14 R13 R12 R11 R10 R9
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Figure 4-57 show that the address map is controlled by the string
Original Mapping of the Address Bits
ROW Address Bits
21 20 19 18 17 16
R8 R7 R6
Remapped Address with TG_TEST
ROW Address Bits
21 20 19 18 17 16
B1 B0 R14 R13 R12 R11 R10 R9
Original Mapping of the Address Bits
21 20 19 18 17
R8 R7 R6 R5 R4
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Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Figure
Figure
15 14 13 12 11 10
R5 R4 R3 R2 R1 R0
15 14 13 12 11 10
R8 C7 C6 C5 R2 R1 R7 R6 R5 C4 C3 C2 C1 C0
BANK
Address
Bits
16 15 14 13 12 11 10
R3 R2 R1 R0 B2 B1 B0
4-56.
4-57.
COLUMN Address Bits
9 8 7 6 5 4 3
C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
COLUMN Address Bits
9 8 7 6 5 4 3
COLUMN Address Bits
9 8 7 6 5 4 3
C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
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2 1 0
2 1 0
2 1 0
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