Xilinx Zynq-7000 User Manual page 238

Table 1-74: DDR2/DDR3 Debug Signals (Cont'd)
Signal Name
dbg_wl_po_fine_cnt_by_dqs
dbg_wl_po_coarse_cnt_by_dqs
dbg_phy_oclkdelay_zfo
dbg_ocal_fuzz2oneeighty
dbg_ocal_fuzz2zero
dbg_ocal_oneeighty2fuzz
dbg_ocal_zero2fuzz
dbg_ocal_oclkdelay_calib_cnt
dbg_ocal_scan_win_not_found
dbg_wrcal_pat_data_match_r
dbg_wrcal_pat_data_match_valid_r
dbg_wrcal_dqs_cnt_r
cal2_state_r
not_empty_wait_cnt
dbg_early1_data
dbg_early2_data
dbg_phy_oclkdelay_cal_57_54
dbg_phy_wrlvl_128_75
dbg_phy_wrlvl_155_129
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
PHASER_OUT Fine Taps found during Write Leveling. Byte capture
based on VIO dbg_dqs setting.
PHASER_OUT Coarse Taps found during Write Leveling. Byte capture
based on VIO dbg_dqs setting.
OCLKDELAY edge found indicator. {z2f, o2f, f2z, f2o}.
Stage 3 tap value of the left-edge of the fall window.
fuzz2zero Stage 3 tap value of the left-edge of the rise window.
oneeighty2fuzz Stage 3 tap value of the right-edge of the fall window.
Stage 3 tap value of the right-edge of the rise window.
DQS group counter indicates which DQS group is in OCLKDELAY
calibration.
Indicator that window is not found during OCLKDELAY calibration.
Asserts when the data pattern match is found during Write Calibration
stage.
Acts as a qualifier and asserts when the data pattern match is valid
during Write Calibration stage.
Current DQS group being calibrated in Write Calibration. When
wrcal_start asserts, wrcal_dqs_cnt_r is 0. The algorithm sequentially
steps through the DQS byte groups checking to see if the read data
pattern matches the expected FF00AA5555AA9966 pattern. If the
pattern matches, wrcal_dqs_cnt increments by 1. The algorithm then
starts looking for the correct data pattern on the next byte until it
reaches DQS_WIDTH – 1 or a data byte group fails due to the data
pattern not being detected properly. The wrcal_dqs_cnt stays at
DQS_WIDTH – 1 after wrcal_done signal is asserted.
Write Calibration state machine variable. States can be decoded in the
ddr_phy_wrcal.v module.
Count value during Write Calibration pattern detection. Maximum
count is 0x1F. If count reaches 0x1F, write calibration fails with the
assertion of dbg_wrcal_err.
Asserts when the pattern detected is one CK clock cycle early. When
this is asserted, the Write Leveling algorithm moves the CK clock one
cycle. After CK is moved, the Write Calibration algorithm restarts
pattern detection.
Asserts when the pattern detected is two CK clock cycles early. When
this is asserted, the Write Leveling algorithm moves the CK clock two
cycles. After CK is moved, the Write Calibration algorithm restarts
pattern detection.
Current DQS group being calibrated from OCLK_DELAY calibration
stage.
PHASER_OUT Fine Taps found during Write Leveling for all bytes
PHASER_OUT Coarse Taps found during Write Leveling for all bytes.
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