Xilinx Zynq-7000 User Manual page 111

UE_FFD[127:96]
This register is only used when the DQ_WIDTH == 144.
Note:
This register stores the (uncorrected) failing data (Bits[127:96]) of the first occurrence of an
access with an uncorrectable error. When the UE_STATUS bit in the ECC Status register is
cleared, this register is re-enabled to store the data of the next uncorrectable error. Storing
of the failing data is enabled after reset.
Table 1-41: Uncorrectable Error First Failing Data [127:96] Register Bit Definitions
Bits Name
31:0 UE_FFD[127:96]
UE_FFE
This register stores the ECC bits of the first occurrence of an access with an uncorrectable
error. When the UE_STATUS bit in the ECC Status register is cleared, this register is
re-enabled to store the ECC of the next uncorrectable error. Storing of the failing ECC is
enabled after reset.
Table 1-42 describes the register bit usage when DQ_WIDTH = 72.
Table 1-42: Uncorrectable Error First Failing ECC Register Bit Definitions for 72-Bit External Memory
Width
Bits Name
31:8 Reserved
7:0 UE_FFE
Table 1-43 describes the register bit usage when DQ_WIDTH = 144.
Table 1-43: Uncorrectable Error First Failing ECC Register Bit Definitions for 144-Bit External Memory
Width
Bits Name
31:16 Reserved
15:0 UE_FFE
FI_D0
This register is used to inject errors in data (Bits[31:0]) written to memory and can be used
to test the error correction and error signaling. The bits set in the register toggle the
corresponding data bits (word 0 or Bits[31:0]) of the subsequent data written to the
memory without affecting the ECC bits written. After the fault has been injected, the Fault
Injection Data register is cleared automatically.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Core Access Reset Value
R 0
Core Access Reset Value
RSVD –
R 0
Core Access Reset Value
RSVD –
R 0
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Description
Data (Bits[127:96]) of the first occurrence of an
uncorrectable error.
Description
Reserved
ECC (Bits[7:0]) of the first occurrence of an
uncorrectable error.
Description
Reserved
ECC (Bits[15:0]) of the first occurrence of an
uncorrectable error.
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