Xilinx Zynq-7000 User Manual page 201

Table 1-68: CK to Address/Control Skew Limit (Cont'd)
FPGA Rating
Rated Actual
1,866
1,600
1,333 1,333
1,066
800
1,866
1,600
1,066 1,333
1,066
800
1,866
1,600
800 1,333
1,066
800
For example, if an 1,863 Mb/s rated FPGA operates at 1600 Mb/s with a 1,600 rated DDR3
component, the CK to address/control skew limit is ±94.1 ps. If a 1,600 Mb/s rated FPGA
operates at 1,066 with a 1,333 rated DDR3 component, the skew limit is ±150 ps.
The skew between bytes in an I/O bank must be 1 ns or less.
Configuration
The XDC contains timing, pin, and I/O standard information. The sys_clk constraint sets
the operating frequency of the interface and is set through the MIG GUI. This must be rerun
if this needs to be altered, because other internal parameters are affected. For example:
create_clock -period 1.875 [get_ports sys_clk_p]
The clk_ref constraint sets the frequency for the IDELAY reference clock, which is
typically 200 MHz. For example:
create_clock -period 5 [get_ports clk_ref_p]
The I/O standards are set appropriately for the DDR3 interface with LVCMOS15, SSTL15,
SSTL15_T_DCI, DIFF_SSTL15, or DIFF_SSTL15_T_DCI, as appropriate. LVDS_25 is used for the
system clock (sys_clk) and I/O delay reference clock (clk_ref). These standards can be
changed, as required, for the system configuration. These signals are brought out to the
top-level for system connection:
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Memory Component Rating
2,133 1,866 1,600
– – –
– – –
75.0 65.0 45.0
150.0 150.0 150.0
150.0 150.0 150.0
– – –
– – –
– – –
147.5 137.5 117.5
150.0 150.0 150.0
– – –
– – –
– – –
– – –
150.0 150.0 150.0
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1,333 1,066 800
– – –
– – –
25.0 – –
150.0 140.4 –
150.0 150.0 150.0
– – –
– – –
– – –
97.5 25.0 –
150.0 150.0 150.0
– – –
– – –
– – –
– – –
150.0 100.0 25.0
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