Xilinx Zynq-7000 User Manual page 607

Read Valid Calibration
During read valid calibration, PHY generates delay count to align the internal Read Valid
with the correct read data. In LPDDR2, WREN to IN_FIFO is tied to 1, which means it is
always writing to the IN_FIFO. The RDEN is tied to inverted registered version of IF_EMPTY,
which means it is always reading once and there is a single entry in IN_FIFO. This soft
calibration is preformed to generate RD_VALID to validate the correct read data from the
SDRAM.
During this stage, PHY perform two sets of three back-to-back writes to a particular bank,
row, and incremental column address. The write data pattern written for the first set of
writes is FF, FF, FF, FF, FF, FF, FF,F F and write data pattern written for the second set of writes
is 55, 55, 55, 55, 55, 55, 55, 55. The data used to perform pattern matching is 55, 55, 55, 55,
55, 55, 55, 55.
During reads, PHY performs three back-to-back reads, with the first and third address used
are the second column address for the first set of writes. The second address used is the
second column address for the second set of writes performed earlier to SDRAM.
The Read Valid state machine waits for a read to occur and then checks if the pattern is
matched. In doing so it also counts the number of cycles used to see the pattern match
(correct data of 55, 55, 55, 55, 55, 55, 55, 55). If the state machine does not see a pattern
match for delay count of 31, it increments the bitslip count, waits and issues another set of
three reads. This process is repeated until either the correct pattern is found and read delay
count is finalized or the bitslip count ≤ 3. If the bitslip count exceeds three, it is considered
a calibration failure.
The bitslip count is fed to select inputs of a MUX which shifts the read data captured from
the output of ISERDESE2 and aligns it to match the entire rise and fall data in the same
cycle.
PRBS Read Leveling
This stage of read calibration follows the Read Leveling calibration stage. The IDELAY tap
setting determined during the Read Leveling calibration stage is used as the starting point
for this stage of calibration. The PRBS read leveling stage does not change the PHASER_IN
fine tap settings determined during the Read Leveling calibration stage.
A 64-bit LFSR generates a 128 long PRBS sequence that is written to the LPDDR2 SDRAM at
the start of this calibration stage. This sequence is then read back continuously to
determine the read data valid window. An averaging algorithm is used for data window
detection where data is read back over multiple cycles at the same tap value. The number of
sampling cycles is set to 36'hFFFFFFFFF. The algorithm starts at the IDELAY tap setting
determined during the Read Leveling calibration stage (initial tap value) and decrements
one tap at time until a data mismatch is found when comparing read data with the expected
data.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
www.xilinx.com
607
Send Feedback