Xilinx Zynq-7000 User Manual page 610

Table 4-24: Memory Controller to Calibration Logic Interface Signals (Cont'd)
Signal Name Width
[CS_WIDTH ×
mc_cs_n nCS_PER_RANK ×
nCK_PER_CLK – 1:0]
mc_cke [nCK_PER_CLK – 1:0]
[2 × nCK_PER_CLK ×
mc_wrdata
DQ_WIDTH – 1:0]
[2 × nCK_PER_CLK ×
mc_wrdata_mask
(DQ_WIDTH/8) – 1:0]
mc_wrdata_en 1
mc_cmd_wren 1
mc_ctl_wren 1
mc_cmd [2:0]
mc_data_offset [5:0]
mc_aux_out0 [3:0]
mc_aux_out1 [3:0]
mc_rank_cnt [1:0]
phy_mc_ctl_full 1
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
I/O
To/From Type Description
PHY
mc_cs_n [CS_WIDTH – 1:0] is the cs_n
Input – associated with the first command in the
sequence.
mc_cke [nCK_PER_CLK – 1:0] is the CKE
associated with the DRAM interface. This
Input –
signal is valid when the CKE_ODT_AUX
parameter is set to FALSE.
This is the write data to the dedicated PHY.
Input –
It is 4x the memory DQ width.
This is the write data mask to the dedicated
Input –
PHY. It is 4x the memory DM width.
Active- This signal is the WREN input to the DQ
Input
High OUT_FIFO.
Active- This signal is the write enable input of the
Input
High address/command OUT_FIFOs.
This signal is the write enable input to the
Active-
Input PHY control word FIFO in the dedicated
High
PHY block.
This signal is used for PHY_Ctl_Wd
configuration:
0x04: Non-data command (No column
Input –
command in the sequence of commands)
0x01: Write command
0x03: Read command
This signal is used for PHY_Ctl_Wd
configuration:
0x00: Non-data command (No column
Input –
command in the sequence of commands)
CWL + COL cmd position: Write command
0x00: Read command
This is the auxiliary outputs field in the PHY
Active-
Input control word used to control ODT and CKE
High
assertion.
This is the auxiliary outputs field in the PHY
Active-
Input control word used to control ODT and CKE
High
assertion for four-rank interfaces.
This is the rank accessed by the command
Input –
sequence in the PHY control word.
Bitwise AND of all the Almost FULL flags of
Active- all the PHY Control FIFOs. The Almost FULL
Output
High flag is asserted when the FIFO is one entry
away from being FULL.
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