Xilinx Zynq-7000 User Manual page 245

Look at dbg_rd_data_offset, dbg_calib_rd_data_offest_1, and
dbg_calib_rd_data_offest _2, these values should vary by one at the most. Next,
compare these values to the values used during normal operation reads on the
dbg_data_offset, dbg_data_offset_1 and dbg_data_offset_2 signals. Record
the results in the "7 Series DDR3 Calibration Results" spreadsheet.
Table 1-75: Debug Signals of Interest for DQSFOUND Calibration
Signal Name
dbg_pi_dqsfound_start
dbg_pi_dqsfound_done
dbg_pi_dqsfound_err
dbg_rd_data_offset_0
dbg_calib_rd_data_offset_1
dbg_calib_rd_data_offset_2
dbg_data_offset
dbg_data_offset_1
dbg_data_offset_2
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
Signifies the start of the DQSFOUND stage of calibration.
Signifies successful completion of the DQSFOUND stage of calibration.
Signifies the DQSFOUND stage of calibration exhibited errors and did not
complete.
Read Data Offset found during calibration.
Read Data Offset found during calibration.
Read Data Offset found during calibration.
Data Offset used during normal operation. Value changes during writes, reads, and
idle. During writes, it is CWL+2+slot#. During non-data commands, it is 0. During
reads, it should match what was found during DQSFOUND calibration
(rd_data_offset_ranks).
Data Offset used during normal operation. Value changes during writes, reads, and
idle. During writes, it is CWL+2+slot#. During non-data commands, it is 0. During
reads, it should match what was found during DQSFOUND calibration
(rd_data_offset_ranks).
Data Offset used during normal operation. Value changes during writes, reads, and
idle. During writes, it is CWL+2+slot#. During non-data commands, it is 0. During
reads, it should match what was found during DQSFOUND calibration
(rd_data_offset_ranks).
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