Xilinx Zynq-7000 User Manual page 313

Table 2-4: Files in user_design/rtl/clocking Directory
(1)
Name
infrastructure.v
clk_ibuf.v
iodelay_ctrl.v
Notes:
1. All file names are prefixed with the MIG version number. For example, for the MIG 4.1 release module name of
clk_ibuf in generated output is now mig_7series_v4_1_clk_ibuf.
user_design/rtl/phy
Table 2-5 lists the files in the user_design/rtl/phy directory:
Table 2-5: Files in user_design/rtl/phy
(1)
Name
qdr_phy_top.v
qdr_phy_write_top.v
qdr_rld_phy_read_top.v
qdr_rld_mc_phy.v
qdr_phy_write_init_sm.v
qdr_phy_write_control_io.v
qdr_phy_write_data_io.v
qdr_rld_prbs_gen.v
qdr_rld_phy_ck_addr_cmd_delay.v
qdr_rld_phy_rdlvl.v
qdr_rld_phy_read_stage2_cal.v
qdr_rld_phy_read_data_align.v
qdr_rld_phy_read_vld_gen.v
qdr_phy_byte_lane_map.v
qdr_rld_phy_4lanes.v
qdr_rld_byte_lane.v
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Description
This module helps in clock generation and distribution.
This module instantiates the system clock input buffers.
This module instantiates the IDELAYCTRL primitive needed for IODELAY use.
Description
This is the top-level module for the physical layer.
This is the top-level wrapper for the write path.
This is the top-level of the read path.
This module is a parameterizable wrapper instantiating up to
three I/O banks each with 4-lane PHY primitives.
This module contains the logic for the initialization state machine.
This module contains the logic for the control signals going to the
memory.
This module contains the logic for the data and byte writes going
to the memory.
This PRBS module uses a many-to-one feedback mechanism for
2n sequence generation.
This module contains the logic to provide the required delay on
the address and control signals
This module contains the logic for stage 1 calibration.
This module contains the logic for stage 2 calibration.
This module realigns the incoming data.
This module contains the logic to generate the valid signal for the
read data returned on the user interface.
This wrapper file handles the vector remapping between the
mc_phy module ports and the user memory ports.
This module is the parameterizable 4-lane PHY in an I/O bank.
This module contains the primitive instantiations required within
an output or input byte lane.
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Chapter 2: QDR II+ Memory Interface Solution
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