Xilinx Zynq-7000 User Manual page 262

Table 1-81: Debug Signals of Interest for PRBS Read Leveling Calibration (Cont'd)
Debug Signal
ref_bit
complex_victim_inc
rd_victim_sel
prbs_state_r1
rd_valid_r2
left_edge_found_pb
right_edge_found_pb
largest_left_edge
smallest_right_edge
fine_delay_incdec_pb
fine_delay_sel
compare_err_pb_latch_r
fine_pi_dec_cnt
match_flag_and
stage_cnt
fine_inc_stage
compare_err_pb_and
right_edge_found
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Signal Description
Signifies that reference bit of the byte which has largest left edge
PHASER_IN tap value.
Indicates the victim increment for internal calibration pattern change.
Signifies the victim selection to get the correct data pattern to
compare during read back.
Signifies the state of PRBS Read Leveling state machine.
Indicates the read out data is valid to use for comparison.
Indicates left edge found for each bit in a byte.
Left_edge_found_pb[0] is for Bit[0] and left_edge_found_pb[7] is for
Bit[7].
Indicates right edge found for each bit in a byte.
right_edge_found_pb[0] is for Bit[0] and right_edge_found_pb[7] is
for Bit[7].
Signifies the left edge tap value of the byte.
Signifies the right edge tap value of the byte.
Indicates the increment of FINEDELAY tap in IDELAY primitive for
each bit in a byte. fine_delay_incdec_pb[0] is for Bit[0] and
fine_delay_incdec_pb[7] is for Bit[7].
Indicates fine_delay_incdec_pb is applied for FINEDELAY in IDELAY
primitive.
Indicates that data mismatch happened for each bit in a byte at a
specific PHASER_IN tap setting. compare_err_pb_latch_r[0] is for
Bit[0] and compare_err_pb_latch_r[7] is for Bit[7].
Signifies the computed decrease value of PHASER_IN tap.
Indicates all bits have data mismatch. Recoded for five consecutive
PHASER_IN tap setting.
Signifies the number of scans with different setting of FINEDELAY in
IDELAY primitive.
Indicates that FINEDELAY in IDELAY primitive is in the increment
stage.
Signifies the data mismatch happened for all bits in a byte.
Indicates the right edge of the byte is found.
www.xilinx.com
262
Send Feedback