Xilinx Zynq-7000 User Manual page 307

X-Ref Target - Figure 2-35
10. This option creates a new Vivado project. Selecting the menu brings up a dialog box,
which guides you to the directory for a new design project. Select a directory (or use the
defaults) and click OK.
This launches a new Vivado project with all example design files and a copy of the IP.
This project has example_top as the Implementation top directory, and sim_tb_top
as the Simulation top directory, as shown in
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Figure 2-35: Open IP Example Design
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
Figure 2-36.
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