Xilinx Zynq-7000 User Manual page 195

through the frequency backbone to the PLL. The system clock input to the PLL must come
from clock capable I/O.
The system clock input can only be used for an interface in the same column. If the clock
came from another column, the additional PLL or MMCM and clock routing required for this
induces too much additional jitter.
Unused outputs from the PLL can be used as clock outputs. Only the settings for these
outputs can be changed. Settings related to the overall PLL behavior and the used outputs
must not be disturbed.
A PLL cannot be shared among interfaces. See
information on allowed PLL parameters.
DDR3 Component PCB Routing
Fly-by routing topology is required for the clock, address, and control lines. Fly-by means
that this group of lines is routed in a daisy-chain fashion and terminated appropriately at
the end of the line. The trace length of each signal within this group to a given component
must be matched. The controller uses write leveling to account for the different skews
between components. This technique uses fewer FPGA pins because signals do not have to
be replicated. The data bus routing for each component should be as short as possible.
Each signal should be routed on a single PCB layer to minimize discontinuities caused by
additional vias.
V
REF
The V includes internal and external:
REF
• Internal V
REF
• External V
REF
external V
REF
This can be done with a resistive divider or by a regulator that tracks this midpoint.
Regulators that supply a fixed reference voltage irrespective of the VDD voltage should
not be used at these data rates. V
spacing to reduce coupling from other intrusive signals. See 7 Series FPGAs PCB Design
and Pin Planning Guide (UG483)
VCCAUX_IO
VCCAUX_IO has two values that can be set to 1.8V or 2.0V depending on memory
performance. If migration occurs between different memory performance or FPGA speed
grades, VCCAUX_IO might need to be its own supply that can be adjusted. For performance
information, see the 7 Series FPGAs Data Sheets
VCCAUX_IO, see 7 Series SelectIO™ Resources User Guide (UG471)
section.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
– Only be used for data rates of 800 Mb/s or below.
– For the maximum specified data rate in a given FPGA speed grade,
must track the midpoint of the VDD supplied to the DRAM and ground.
REF
[Ref
www.xilinx.com
Clocking Architecture, page 119
traces need to have a larger than the minimum
12], "V Stabilization Capacitors" section.
REF
[Ref 13]. For more information on
for
[Ref 2], "VCCAUX_IO"
195
Send Feedback