Xilinx Zynq-7000 User Manual page 477

Table 3-24: RLDRAM II I/O Standards
Signal
rld_ck_p, rld_ck_n
rld_dk_p, rld_dk_n
rld_cs_n
rld_we_n
rld_ref_n
rld_a
rld_ba
rld_dm
rld_dq
rld_qk_p, rld_qk_n
Table 3-25: RLDRAM 3 I/O Standards
Signal
rld_ck_p, rld_ck_n
rld_dk_p, rld_dk_n
rld_cs_n
rld_we_n
rld_ref_n
rld_a
rld_ba
rld_dm
rld_dq
rld_qk_p, rld_qk_n
DCI (HP banks) or IN_TERM (HR banks) is required at the FPGA to meet the specified
performance. Designs generated by the MIG tool use the DCI standards for Data (DQ) and
Read Clock (QK_P and QK_N) in the High-Performance banks. In the High-Range banks for
RLDRAM II, the MIG tool uses the HSTL_II and DIFF_HSTL_II standards with the internal
termination (IN_TERM) attribute chosen in the GUI.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Direction I/O Standard
Output DIFF_HSTL_I
InOut DIFF_HSTL_II
Output HSTL_I
Output HSTL_I
Output HSTL_I
Output HSTL_I
Output HSTL_I
Output HSTL_I
Input/Output HSTL_II_T_DCI, HSTL_II
Input DIFF_HSTL_II_DCI, DIFF_HSTL_II
Direction I/O Standard
Output DIFF_SSTL12
InOut DIFF_SSTL12
Output SSTL12
Output SSTL12
Output SSTL12
Output SSTL12
Output SSTL12
Output SSTL12
Input/Output SSTL12_T_DCI, SSTL12
Input DIFF_SSTL12_DCI, DIFF_SSTL12
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