Xilinx Zynq-7000 User Manual page 444

Figure 3-49 shows the alignment of the various clocks and how they are used to generate
the necessary signal alignment.
X-Ref Target - Figure 3-49
OCLK_DELAYED generates a center-aligned clock for DDR write data but it does not produce
an ideal alignment for SDR address/control signals. For this reason, OCLK is used to
generate CK/CK#, and depending on if calibration must be done on the write datapath
either the address/control byte lanes are shifted or data byte lanes are shifted, to properly
align the memory clock CK and the write clock DK. For certain frequencies a one-time
calibration is performed for OCLK_DELAYED to ensure reliable write operations. For details,
see the Calibration
The OUT_FIFO serves as a temporary buffer to convert the write data from the FPGA logic
domain to the PHASER clock domain, which clocks out the output data from the I/O logic.
The OUT_FIFO runs in asynchronous mode, with the read and write clocks running at the
same frequency yet an undetermined phase. A shallow, synchronous PRE_FIFO drives the
OUT_FIFO with continuous data from the FPGA logic in an event of a flag assertion from the
OUT_FIFO, which might potentially stall the flow of data through the OUT_FIFO. The clocks
required for operating the OUT_FIFOs and OSERDES are provided by PHASER_OUT_PHY.
The clocking details of the write paths using PHASER_OUT_PHY are shown in
The PHY Control block is used to ensure proper start-up of all PHASER_OUT_PHY blocks
used in the interface as well as to control the 3-state timing for RLDRAM 3 operation.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Figure 3-49: Write Path Output Alignment
section.
www.xilinx.com
Figure 3-50.
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