Xilinx Zynq-7000 User Manual page 80

Table 1-14: Signals of Interest During Simulation for the AXI4 Test Bench
Signal
dbg_rd_sts_vld
dbg_rd_sts
The initialization and the calibration sequence remain the same as that indicated in
Simulating the Example Design (for Designs with the Standard User Interface), page
status that is generated for a write transaction can be found in
X-Ref Target - Figure 1-44
Table 1-15: Debug Status for the Write Transaction
Bits Description
39:32 Number of beats/write transfers completed for last burst
31:21 Reserved
Data pattern used for the current transaction:
• 000: 5A and A5
• 001: PRBS pattern
20:18 • 010: Walking zeros
• 011: Walking ones
• 100: All ones
• 101: All zeros
17 Write error occurred. The write transaction could not be completed.
16 Command error occurred during a write transaction.
15:9 Reserved
AXI wrapper write FSM state when timeout (watchdog timer should be enabled) occurs:
• 3'b001: Data write transaction
8:6 • 3'b010: Waiting for acknowledgment for written data
• 3'b011: Dummy data write transaction
• 3'b100: Waiting for response from the response channel
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
When asserted, this signal indicates a valid status for the read transaction on the
dbg_rd_sts bus. This signal is asserted even if the read transaction does not
complete.
This signal has the status of the read transaction. The details of the status are given
in Table 1-16.
Figure 1-44: Status for the Write Transaction
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66. The
Figure 1-44.
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