Xilinx Zynq-7000 User Manual page 175

A detailed description of the PHY architecture and the various stages of calibration are
provided in PHY, page
the PHY are listed in
For clocking requirements, see
infrastructure, iodelay_ctrl, and clk_ibuf modules provided in the clocking directory
output by the MIG tool or instantiate the primitives in these modules in your system design.
In 2014.4, the OCLKDELAYED calibration stage was enhanced to optimize the calibration
center point using MMCM phase shift taps. This resulted in the addition of a BUFG for the
distribution of the phase shifted clock output and a few input and output ports between the
PHY and the infrastructure module. These additional ports are listed in
The tempmon module in the clocking directory should be used to supply the temperature
data from the XADC to the ddr_phy_tempmon module. For more information, see
Temperature Monitor, page
The PHY Control FIFO, command OUT_FIFOs, and write data OUT_FIFOs are all in
asynchronous operation mode. The read clock and the write clock to these FIFOs differ in
frequency and phase. Therefore all three OUT_FIFO FULL flags (phy_mc_ctl_full,
phy_mc_cmd_full, and phy_mc_data_full) described in
monitored by the controller to prevent overflow of the PHY Control FIFO and the
OUT_FIFOs, leading to loss of command and data.
Memory commands and data can be sent directly through the PHY interface. Different
command types are sent through different slots. The CAS Write Latency (CWL) command
dictates the slot number to use for write/read commands. For an odd CWL value, CAS slot
numbers 1 or 3 can be used; for an even CWL value, CAS slot numbers 0 or 2 can be used
for the write/read commands. In
Seq, and Act Pre fields of PHY Control words are tied Low internally inside the phy_top
module and are not used.
Note that the following inputs have to be tied to logic "1."
IMPORTANT:
assign mc_reset_n = 1'b1;
assign mc_cmd_wren = 1'b1;
assign mc_ctl_wren = 1'b1;
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
131. The signals required for the Memory Controller to interface to
Table 1-61.
Clocking Architecture, page
158.
Figure 1-88, the Control Offset, Low Index, Event Delay,
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119. You can choose to use the
Table 1-61.
Table 1-61, page 159
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must be
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