Xilinx Zynq-7000 User Manual page 443

Write Path
The write path to the RLDRAM II/RLDRAM 3 includes the address, data, and control signals
necessary to execute any memory operation. The control strobes rld_cs_n, rld_we_n,
rld_ref_n, and rld_reset_n (RLDRAM 3 only), including addresses rld_a and rld_ba
to the memory all use SDR formatting. The write data values rld_dq and rld_dm also use
DDR formatting to achieve the required two/four/eight-word burst within the given clock
periods.
Output Architecture
The output path of the RLDRAM II/RLDRAM 3 interface solution uses OUT_FIFOs,
PHASER_OUT_PHY, PHY_CNTRL, and OSERDES primitives available in 7 series FPGAs. These
blocks are used for clocking all outputs of the PHY to the memory device.
The PHASER_OUT_PHY block provides the clocks required to clock out the outputs to the
memory. It provides synchronized clocks for each byte group, to the OUT_FIFOs and to the
OSERDES/ODDR. PHASER_OUT_PHY generates the byte clock (OCLK), the divided byte clock
(OCLKDIV), and a delayed byte clock (OCLK_DELAYED) for its associated byte group. The
byte clock (OCLK) is the same frequency as the memory interface clock and the divided byte
clock (OCLKDIV) is half the frequency of the memory interface clock. The byte clock (OCLK)
is used to clock the Write data (DQ), Data Mask (DM), Address, controls, and system clock
(CK/CK#) signals to the memory from the OSERDES/ODDR. The PHASER_OUT_PHY output,
OCLK_DELAYED, is an adjustable phase-shifted output with respect to the byte clock (OCLK)
and is used to generate the write clock (DK/DK#) to the memory.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
www.xilinx.com
443
Send Feedback