Xilinx Zynq-7000 User Manual page 227

Table 1-72: 72-Bit DDR3 UDIMM Interface in Three Banks (Cont'd)
Bank Signal Name
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Byte Group
DQ11 B_05
DQ10 B_04
DQ9 B_03
DQ8 B_02
DM1 B_01
– B_00
DQ7 A_11
DQ6 A_10
DQ5 A_09
DQ4 A_08
DQS0_P A_07
DQS0_N A_06
DQ3 A_05
DQ2 A_04
DQ1 A_03
DQ0 A_02
DM0 A_01
RESET_N A_00
VRN –
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I/O Type I/O Number
P 18
N 17
P 16
N 15
P 14
N 13
P 12
N 11
P 10
N 9
P 8
N 7
P 6
N 5
P 4
N 3
P 2
N 1
SE 0
Special
Designation
–
–
–
–
–
–
–
–
–
–
DQS-P
DQS-N
–
–
–
–
–
–
–
227
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