Xilinx Zynq-7000 User Manual page 478

Clocking
The 7 series FPGA MIG RLDRAM II/RLDRAM 3 design has two clock inputs, the reference
clock and the system clock. The reference clock drives the IODELAYCTRL components in the
design, while the system clock input is used to create all MIG design clocks that are used to
clock the internal logic, the frequency reference clocks to the phasers, and a
synchronization pulse required for keeping PHY control blocks synchronized in multi-I/O
bank implementations. For more information on clocking architecture, see
Architecture, page
The MIG tool allows you to input the Memory Clock Period and then lists available Input
Clock Periods that follow the supported clocking guidelines. Based on these two clock
periods selections, the generated MIG core appropriately sets the PLL parameters. The MIG
tool enables automatic generation of all supported clocking structures. For information on
how to use the MIG tool to set up the desired clocking structure including input clock
placement, input clock frequency, and IDELAYCTRL ref_clk generation, see
Series FPGAs RLDRAM II/RLDRAM 3 Memory Design, page
Input Clock Guidelines
The input system clock cannot be generated internally.
IMPORTANT:
• PLL Guidelines
CLKFBOUT_MULT_F (M) must be between 1 and 16 inclusive.
°
DIVCLK_DIVIDE (D, Input Divider) can be any value supported by the PLLE2
°
parameter.
CLKOUT_DIVIDE (O, Output Divider) must be 2 for 400 MHz and up operation and 4
°
for below 400 MHz operation.
The above settings must ensure the minimum PLL VCO frequency (FVCOMIN) is
°
met. For specifications, see the appropriate DC and Switching Characteristics Data
Sheet. The 7 Series FPGAs Clocking Resources User Guide (UG472)
the equation for calculating FVCO.
The relationship between the input period and the memory period is InputPeriod =
°
(MemoryPeriod × M)/(D × D1).
• The clock input (sys_clk) can be input on any CCIO in the column where the memory
interface is located; this includes CCIO in banks that do not contain the memory
interface, but must be in the same column as the memory interface. The PLL must be
located in the bank containing the clock sent to the memory. To route the input clock
to the memory interface PLL, the CMT backbone must be used. With the MIG
implementation, one spare interconnect on the backbone is available that can be used
for this purpose.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
434.
www.xilinx.com
Clocking
Creating the 7
390.
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