Xilinx Zynq-7000 User Manual page 265

Table 1-83: Debug Signals Used for Configuring the Traffic Generator (Cont'd)
Signal Name
vio_data_mode_value
Notes:
1. This setting does not work by default and additional RTL modifications are required.
Table 1-84: Debug Signals of Interest When Isolating Data Error Using the Traffic Generator
Signal Name Description
Read data read out of the IN_FIFO for the DQS group selected through dbg_dqs on the VIO.
dbg_rddata_r
This is a 64-bit bus. This debug port does not capture ECC data.
cmp_data_r Expected data to be compared with read back data from memory.
dbg_rddata_valid Signifies that the read data is valid.
cmp_data_valid Signifies the compare data is valid.
cmp_error Signifies the cmp_data is not the same as the readback data from memory.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
Valid settings for this signal are:
• 0x0 = Reserved
• 0x1 = FIXED – 32 bits of fixed_data as defined through fixed_data_i inputs.
• 0x2 = ADDRESS – 32 bits address as data. Data is generated based on the logical
address space. If a design has a 256-bit user data bus, each write beat in the user bus
would have a 256/8 address increment in byte boundary. If the starting address is
1300, the data is 1300, followed by 1320 in the next cycle. To simplify the logic, the
user data pattern is a repeat of the increment of the address value Bits[31:0].
• 0x3 = HAMMER – All 1s are on DQ pins during the rising edge of DQS, and all 0s are
on the DQ pins during the falling edge of DQS, except the VICTIM line as defined in
the parameter "SEL_VICTIM_LINE." This option is only valid if parameter
DATA_PATTERN = "DGEN_HAMMER" or "DGEN_ALL."
• 0x4 = SIMPLE8 – Simple 8 data pattern that repeats every 8 words. The patterns can
be defined by the "simple_datax" inputs.
• 0x5 = WALKING1s – Walking 1s are on the DQ pins. The starting position of 1
depends on the address value. This option is only valid if the parameter
DATA_PATTERN = "DGEN_WALKING" or "DGEN_ALL."
• 0x6 = WALKING0s – Walking 0s are on the DQ pins. The starting position of 0
depends on the address value. This option is only valid if the parameter
DATA_PATTERN = "DGEN_WALKING0" or "DGEN_ALL."
• 0x7 = PRBS – A 32-stage LFSR generates random data and is seeded by the starting
address. This option is only valid if the parameter DATA_PATTERN = "DGEN_PRBS" or
"DGEN_ALL."
• 0x9 = SLOW HAMMER – This is the slow MHz hammer data pattern.
• 0xF = PHY_CALIB pattern – 0xFF, 00, AA, 55, 55, AA, 99, 66. This mode only generates
READ commands at address zero. This is only valid in the Virtex-7 family.
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