Xilinx Zynq-7000 User Manual page 324

Table 2-8 lists the signals used in the infrastructure module that provides the necessary
clocks and reset signals required in the design.
Table 2-8: Infrastructure Clocking and Reset Signals
Signal Direction Description
mmcm_clk Input
sys_rst Input
iodelay_ctrl_rdy Input
clk Output
mem_refclk Output
freq_refclk Output
sync_pulse Output
pll_locked Output
rstdiv0 Output
Physical Interface
The physical interface is the connection from the FPGA memory interface solution to an
external QDR II+ SRAM device. The I/O signals for this interface are shown in
These signals can be directly connected to the corresponding signals on the QDR II+ SRAM
device.
Table 2-9: Physical Interface Signals
Signal Direction
qdr_cq_n Input
qdr_cq_p Input
qdr_d Output
qdr_dll_off_n Output
qdr_bw_n Output
qdr_k_n InOut
qdr_k_p InOut
qdr_q Input
qdr_sa Output
qdr_w_n Output
qdr_r_n Output
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
System clock input.
Core reset from user application.
IDELAYCTRL lock status.
Half frequency FPGA logic clock.
PLL output clock at same frequency as the memory clock.
PLL output clock to provide the FREQREFCLK input to the Phaser. The freq_refclk is
generated such that its frequency in the range of 400 MHz to 1,066 MHz.
PLL output generated at 1/16 of mem_Refclk and is a synchronization signal sent
to the PHY hard blocks that are used in a multi-bank implementation.
Locked output from PLLE2_ADV.
Reset output synchronized to internal FPGA logic half frequency clock.
Description
QDR CQ#. This is the echo clock returned from the memory derived from
qdr_k_n.
QDR CQ. This is the echo clock returned from the memory derived from
qdr_k_p.
QDR Data. This is the write data from the PHY to the
device.
QDR DLL Off. This signal turns off the DLL in the memory device.
QDR Byte Write. This is the byte write signal from the PHY to the QDR II+
SRAM device.
QDR Clock K#. This is the inverted input clock to the memory device.
QDR Clock K. This is the input clock to the memory device.
QDR Data Q. This is the data returned from reads to memory.
QDR Address. This is the address supplied for memory operations.
QDR Write. This is the write command to memory.
QDR Read. This is the read command to memory.
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Chapter 2: QDR II+ Memory Interface Solution
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Table 2-9.
QDR II+ memory
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