Xilinx Zynq-7000 User Manual page 411

mig_7series_v4_1
docs
example_design
par
rtl
sim
synth
user_design
rtl
xdc
Directory and File Contents
The 7 series FPGAs core directories and their associated files are listed in this section for
Vivado implementations.
<component name>/example_design/
The example_design directory structure contains all necessary RTL, constraints, and
script files for simulation and implementation of the complete MIG example design with a
test bench.
Table 3-1 lists the files in the example_design/rtl directory.
Table 3-1: Files in example_design/rtl Directory
Name
example_top.v
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
traffic_gen
clocking
controller
ip_top
phy
ui
Description
This top-level module serves as an example for connecting the user design to
the 7 series FPGAs memory interface core.
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