Xilinx Zynq-7000 User Manual page 574

3. Apply the settings and select OK.
X-Ref Target - Figure 4-43
4. In the Flow Navigator window, select Run Simulation and select Run Behavioral
Simulation as shown in
5. Vivado invokes IES and simulations are run in the IES tool. For more information, see the
Vivado Design Suite User Guide: Logic Simulation (UG900)
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Figure 4-43: Simulation with IES
Figure 4-40.
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[Ref 8].
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