Xilinx Zynq-7000 User Manual page 103

Table 1-21: AXI4-Lite Slave Control/Status Register Parameters
Parameter Name
C_S_AXI_CTRL_ADDR_WIDTH
C_S_AXI_CTRL_DATA_WIDTH
C_ECC_ONOFF_RESET_VALUE
C_S_AXI_CTRL_BASEADDR
C_S_AXI_CTRL_HIGHADDR
C_S_AXI_CTRL_PROTOCOL
AXI4-Lite Slave Control/Status Register Interface Signals
Table 1-22 lists the AXI4 slave interface specific signals. Clock/reset to the interface is
provided from the Memory Controller.
Table 1-22: List of New I/O Signals
Name Width
s_axi_ctrl_awaddr C_S_AXI_CTRL_ADDR_WIDTH
s_axi_ctrl_awvalid 1
s_axi_ctrl_awready 1
s_axi_ctrl_wdata C_S_AXI_CTRL_DATA_WIDTH
s_axi_ctrl_wvalid 1
s_axi_ctrl_wready 1
s_axi_ctrl_bvalid 1
s_axi_ctrl_bready 1
s_axi_ctrl_araddr C_S_AXI_CTRL_ADDR_WIDTH
s_axi_ctrl_arvalid 1
s_axi_ctrl_arready 1
s_axi_ctrl_rdata C_S_AXI_CTRL_DATA_WIDTH
s_axi_ctrl_rvalid 1
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Default Allowable
Value Values
32 32, 64
32 32
1 0, 1
– Valid Address
– Valid Address
AXI4LITE AXI4LITE
Direction
Input
Input
Output
Input
Input
Output
Output
Input
Input
Input
Output
Output
Output
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Description
This is the width of the AXI4-Lite address buses.
This is the width of the AXI4-Lite data buses.
Controls ECC on/off value at startup/reset.
This parameter specifies the base address for
the AXI4-Lite slave interface.
This parameter specifies the high address for
the AXI4-Lite slave interface.
AXI4-Lite protocol
Active
Description
State
Write address.
Write address valid. This signal
indicates that valid write address
High
and control information are
available.
Write address ready. This signal
indicates that the slave is ready to
High
accept an address and associated
control signals.
Write data
Write valid. This signal indicates that
High
write data and strobe are available.
High Write ready.
High Write response valid.
High Response ready.
Read address.
High Read address valid.
High Read address.
Read data.
Read valid.
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