Xilinx Zynq-7000 User Manual page 138

Table 1-59: Auxiliary Output Attributes
Attribute
MC_AO_WRLVL_EN
WR_CMD_OFFSET_0
WR_DURATION_0
RD_CMD_OFFSET_0
RD_DURATION_0
WR_CMD_OFFSET_1
WR_DURATION_1
RD_CMD_OFFSET_1
RD_DURATION_1
WR_CMD_OFFSET_2
WR_DURATION_2
RD_CMD_OFFSET_2
RD_DURATION_2
WR_CMD_OFFSET_3
WR_DURATION_3
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Type Description
This attribute specifies whether or not the related Aux_Output is active
during write leveling as specified by the PC_Enable_Calib[1] signal. For
Vector[3:0]
example, this attribute specifies whether ODT is active during write
leveling.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
after the associated write command is executed that the auxiliary output
Vector[5:0] becomes active. For example, this attribute ensures that the ODT signal
is asserted at the correct clock cycle to meet the JEDEC ODTLon and
ODTLoff specifications.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
the auxiliary output remains active for a write command. For example,
Vector[5:0]
this attribute ensures that the ODT signal is asserted at the correct clock
cycle to meet the JEDEC ODTLon and ODTLoff specifications.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0] after the associated read command is executed that the auxiliary output
becomes active.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0]
the auxiliary output remains active for a read command.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0] after the associated write command is executed that the auxiliary output
becomes active.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0]
the auxiliary output remains active for a write command.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0] after the associated read command is executed that the auxiliary output
becomes active.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0]
the auxiliary output remains active for a read command.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0] after the associated write command is executed that the auxiliary output
becomes active.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0]
the auxiliary output remains active for a write command.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0] after the associated read command is executed that the auxiliary output
becomes active.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0]
the auxiliary output remains active for a read command.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0] after the associated write command is executed that the auxiliary output
becomes active.
This attribute specifies how long in DDR2 or DDR3 SDRAM clock cycles
Vector[5:0]
the auxiliary output remains active for a write command.
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