Xilinx Zynq-7000 User Manual page 164

Table 1-62: AXI Byte Address Masking (Cont'd)
PHY to MC Clock
Ratio
2:1
Upsizing
When the data width on the User Interface side is wider than that on the AXI Interface side,
upsizing is performed in the AXI Shim interface. Data packing is performed for INCR and
WRAP bursts.
In the resulting transaction issued to the user interface side, the number of data beats is
reduced accordingly:
• For writes, data merging occurs.
• For reads, data serialization occurs.
User Interface
The mapping between the User Interface address bus and the physical memory row, bank
and column can be configured. Depending on how the application data is organized,
addressing scheme Bank- Row-Column or Row-Bank-Column can be chosen to optimize
controller efficiency. These addressing schemes are shown in
X-Ref Target - Figure 1-72
Figure 1-72: Memory Address Mapping for Bank-Row-Column Mode in UI Module
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Memory Interface
UI Data Width
Data Width
32
64
128
256
www.xilinx.com
AXI Byte Address [7:0] (LSBs)
8
16
32
64 A[7:3], 3'b000
Figure 1-72
Masking
A[7:0]
A[7:1], 1'b0
A[7:2], 2'b00
and Figure 1-73.
164
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