Xilinx Zynq-7000 User Manual page 109

Table 1-34 describes the register bit usage when DQ_WIDTH = 72.
Table 1-34: Correctable Error First Failing ECC Register Bit Definitions for 72-Bit External Memory
Width
Bits Name
31:8 Reserved
7:0 CE_FFE
Table 1-35 describes the register bit usage when DQ_WIDTH = 144.
Table 1-35: Correctable Error First Failing ECC Register Bit Definitions for 144-Bit External Memory
Width
Bits Name
31:16 Reserved
15:0 CE_FFE
UE_FFA[31:0]
This register stores the address (Bits[31:0]) of the first occurrence of an access with an
uncorrectable error. When the UE_STATUS bit in the ECC Status register is cleared, this
register is re-enabled to store the address of the next uncorrectable error. Storing of the
failing address is enabled after reset.
Table 1-36: Uncorrectable Error First Failing Address [31:0] Register Bit Definitions
Bits Name
31:0 UE_FFA [31:0]
UE_FFA[63:32]
This register is unused if C_S_AXI_ADDR_WIDTH < 33.
Note:
This register stores the address (Bits[63:32]) of the first occurrence of an access with an
uncorrectable error. When the UE_STATUS bit in the ECC Status register is cleared, this
register is re-enabled to store the address of the next uncorrectable error. Storing of the
failing address is enabled after reset.
Table 1-37: Uncorrectable Error First Failing Address [31:0] Register Bit Definitions
Bits Name
31:0 UE_FFA[63:32]
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Core Access Reset Value
RSVD –
R 0
Core Access Reset Value
RSVD –
R 0
Core Access Reset Value
R 0
Core Access Reset Value
R 0
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Description
Reserved
ECC (Bits[7:0]) of the first occurrence of a correctable
error.
Description
Reserved
ECC (Bits[15:0]) of the first occurrence of a
correctable error.
Description
Address (Bits[31:0]) of the first occurrence of an
uncorrectable error.
Description
Address (Bits[63:32]) of the first occurrence of an
uncorrectable error
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