Xilinx Zynq-7000 User Manual page 205

• For data widths of 16 with a x8 part, only one set of CK/CK#, CS, ODT ports is generated
to fit the design in a single bank.
• VRN and VRP are used for the digitally controlled impedance (DCI) reference for banks
that support DCI. DCI cascade is permitted.
• The interface must be arranged vertically.
• No more than three banks can be used for a single interface. All the banks chosen must
be consequent.
• The system clock input must be in the same column as the memory interface. The
system clock input is recommended to be in the address/control bank, when possible.
RECOMMENDED:
(SLRs), it is not recommended due to the additional clock jitter in this topology.
• Devices implemented with SSI technology have SLRs. Memory interfaces cannot span
across SLRs. Ensure that this rule is followed for the part chosen and for any other
pin-compatible parts that can also be used.
Bank Sharing Among Controllers
No unused part of a bank used in a memory interface is permitted to be shared with
another memory interface. The dedicated logic that controls all the FIFOs and phasers in a
bank is designed to only operate with a single memory interface and cannot be shared with
other memory interfaces.
Pin Swapping
• Pins can be freely swapped within each byte group (data and address/control), except
for the DQS pair which must be on a clock-capable DQS pair and the CK, which must be
on a p-n pair.
• Byte groups (data and address/control) can be freely swapped with each other.
• Pins in the address/control byte groups can be freely swapped within and between
their byte groups.
• No other pin swapping is permitted.
Internal V
REF
Internal V can only be used for data rates of 800 Mb/s or below.
REF
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Although the MIG allows system clock selection to be in different super logic regions
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