Xilinx Zynq-7000 User Manual page 243

Table 1-74: DDR2/DDR3 Debug Signals (Cont'd)
Signal Name
dbg_po_counter_read_val
dbg_mem_pattern_init_done
dbg_tg_compare_error
dbg_tg_wr_data_counts
dbg_tg_rd_data_counts
Debugging PHASER_IN PHASELOCKED Calibration Failures
(dbg_pi_phaselock_err = 1)
Calibration Overview
During this stage of calibration, each PHASER_IN is placed in the read calibration mode to
phase align its free-running frequency reference clock to the associated read DQS. The
calibration logic issues back-to-back read commands to provide the PHASER_IN block with
a continuous stream of DQS pulses for it to achieve lock. Each DQS has an associated
PHASER_IN block. dbg_pi_phase_locked asserts when all PHASER_INs have achieved
lock and the PHASER_INs are then placed in normal operation mode.
Debug
If PHASER_IN PHASELOCKED calibration failed, probe the DQS at the memory. A continuous
stream of DQS pulses must be seen for lock to occur. Verify the signal integrity of the DQS
pulses.
Debugging PHASER_IN DQSFOUND Calibration Failures
(dbg_pi_dqsfound_err = 1)
Calibration Overview
In this stage of calibration, the different DQS groups in an I/O bank are aligned to the same
PHY_Clk and the optimal read data offset position is found with respect to the read
command. The calibration logic issues a set of four back-to-back reads with gaps in
between. Each PHASER_IN detects the read DQS preamble. A single read data offset value is
determined for all DQS groups in an I/O bank. The PHASER_OUT stage 2 delay for
CK/Address/Command/Control byte lanes are increased and decreased to improve margin
on the read DQS preamble detected. This read data offset is then used during read requests
to the PHY_CONTROL block.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
See Table 1-85.
Signal that indicates initial write to the memory is completed.
Sticky bit indicating the error in data transfer after calibration is done.
Counter for the number of bytes written by the Traffic Generator.
Counter for the number of bytes read by the Traffic Generator.
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