Xilinx Zynq-7000 User Manual page 467

This generates a file named flight_time.csv in the current directory with package trace
delay information for each pin. While applying specific trace-matching guidelines for the
RLDRAM II/RLDRAM 3 interface, this additional package delay term should be considered
for the overall electrical propagation delay. Different die in the same package might have
different delays for the same package pin. If this is expected, the values should be averaged
appropriately. This decreases the maximum possible performance for the target device.
These rules indicate the maximum electrical delays between RLDRAM II/RLDRAM 3 signals:
• RLDRAM II
For x36 data width, the maximum skew between DQ[17:0] and DK/DK#[0] should be
°
±15 ps.
For x36 data width, the maximum skew between DQ[35:18] and DM and DK/DK#[1]
°
should be ±15 ps.
For x18 data width, the maximum skew between any DQ/DM and DK/DK# should be
°
±15 ps.
• RLDRAM 3
The maximum skew between DQ[8:0] and DQ[26:18] and DM[0] to DK/DK#[0]
°
should be ±15 ps.
The maximum skew between DQ[17:9] and DQ[35:27] and DM[1] to DK/DK#[1]
°
should be ±15 ps.
• The maximum skew between any DQ and its associated QK/QK# should be:
RLDRAM II: ±15 ps
°
RLDRAM 3: ±10 ps
°
• The maximum skew between any address and control signals and the corresponding
CK/CK# should be ±50 ps.
• The maximum skew between any DK/DK# and CK/CK# should be ±25 ps.
Pinout Requirements
Xilinx 7 series FPGAs are designed for very high-performance memory interfaces, and
certain rules must be followed to use the RLDRAM II/RLDRAM 3 physical layer. Xilinx 7
series FPGAs have dedicated logic for each byte group. Four byte groups are available in
each 50-pin bank. Each 50-pin bank consists of two pairs of multiregion clock capable I/O
(MRCC) pins and four byte groups that contain 1 DQS clock-capable I/O pair and 10
associated I/Os.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
www.xilinx.com
467
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