Xilinx Zynq-7000 User Manual page 266

Table 1-84: Debug Signals of Interest When Isolating Data Error Using the Traffic Generator (Cont'd)
Signal Name Description
This signal latches these values when the error signal is asserted:
• [42] = mcb_rd_empty
error_status[n:0] • [41] = mcb_wr_full
• [37:32] = cmp_bl_i
• [31:0] = cmp_addr_i
Notes:
1. Cmp_data_r is not cycle aligned with dbg_rddata_r and might vary from 1 burst before to 3 bursts after dbg_rddata_r.
Isolating the Data Error
Using either the MIG 7 series Traffic Generator or the user design, the first step in data error
debug is to isolate when and where the data errors occur. To perform this, the expected data
and actual data must be known and compared. Looking at the data errors, the following
should be identified:
• Are the errors bit or byte errors?
Are errors seen on data bits belonging to certain DQS groups?
°
Are errors seen on specific DQ bits?
°
• Is the data shifted, garbage, swapped, and others?
• Are errors seen on accesses to certain addresses, banks, or ranks of memory?
Designs that can support multiple varieties of DIMM modules, all possible address
°
and bank bit combinations should be supported.
• Do the errors only occur for certain data patterns or sequences?
This can indicate a shorted or open connection on the PCB. It can also indicate an
°
SSO or crosstalk issue.
• Determine the frequency and reproducibility of the error.
Does the error occur on every calibration/reset?
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Does the error occur at specific temperature or voltage conditions?
°
• Determine if the error is correctable.
Rewriting, rereading, resetting, and recalibrating.
°
To isolate the data error using the MIG 7 series Example Design Traffic Generator, use the
following steps.
• Determine what type of data error is being seen (bit or byte errors).
a. Set the ILA trigger to cmp_error = 1.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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