Xilinx Zynq-7000 User Manual page 8

Date Version
12/18/2013 2.0
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
• Vivado Design Suite release only for MIG v2.0.
Chapter 1
• Added Out of Context content.
• Updated Table 1-4: Modules in example_design/sim Directory.
• Updated <component name>/user_design section.
• Updated Fig. 1-39: Synthesizable Example Design Block Diagram.
• Added simulator flows.
• Added Bits[39:32] to Table 1-15: Debug Status for the Write Transaction.
• Added Bits[39:32] to Table 1-16: Debug Status for the Read Transaction.
• Added OOC description in Customizing the Core section.
• Added ILA trigger settings in Vivado Lab Tools section.
• Added note on read latency in Debug section.
• Updated Chipscope triggers to R in Debug section.
Chapter 2
• Added Out of Context content.
• Updated Table 2-3: Modules in example_design/sim Directory.
• Updated <component name>/user_design section.
• Added OOC description in Customizing the Core section.
• Added simulator flows.
• Added ILA trigger settings in Vivado Lab Tools section.
Chapter 3
• Added Out of Context content.
• Updated Table 3-3: Modules in example_design/sim Directory.
• Updated <component name>/user_design section.
• Updated Fig. 3-35: Synthesizable Example Design Block Diagram.
• Added OOC description in Customizing the Core section.
• Added simulator flows.
• Added ILA trigger settings in Vivado Lab Tools section.
• Updated Fig. 3-48 Write Path Block Diagram of the RLDRAM II Interface Solution.
• Added note on read latency in Debug section.
Chapter 4
• Added Out of Context content.
• Updated Table 4-4: Modules in example_design/sim Directory.
• Updated <component name>/user_design section.
• Updated Fig. 4-37: Synthesizable Example Design Block Diagram.
• Added OOC description in Customizing the Core section.
• Added simulator flows.
• Added note on read latency in Debug section.
Chapter 5
• Added Out of Context content.
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