Xilinx Zynq-7000 User Manual page 486

3. In the Flow Navigator window, select Run Simulation and select Run Behavioral
Simulation as shown in
X-Ref Target - Figure 3-65
RLDRAM 3 memory model has System Verilog constructs, which are not supported by Vivado
Note:
Simulator.
Simulation Flow Using Questa Advanced Simulator
1. In the Open IP Example Design Vivado project, under Flow Navigator select
Simulation Settings.
2. Select Target simulator as Questa Advanced Simulator/ModelSim.
a. Browse to the Compiled libraries location and set the path on Compiled libraries
location option.
b. Under the Simulation tab, set the modelsim.simulate.runtime to 1 ms (there
are simulation RTL directives which stop the simulation after certain period of time,
which is less than 1 ms), set modelsim.simulate.vsim.more_options to
-novopt as shown in
c. Under Compilation tab, set modelsim.compile.vlog.more_options to -sv
(only for RLDRAM 3 designs).
3. Apply the settings and select OK.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Figure 3-65.
Figure 3-65: Run Behavioral Simulation
Figure 3-64.
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