Xilinx Zynq-7000 User Manual page 100

Arbitration in AXI Shim
The AXI4 protocol calls for independent read and write address channels. The Memory
Controller has one address channel. The following arbitration options are available for
arbitrating between the read and write address channels.
Time Division Multiplexing (TDM)
Equal priority is given to read and write address channels in this mode. The grant to the
read and write address channels alternate every clock cycle. The read or write requests from
the AXI master has no bearing on the grants. For example, the read requests are served in
alternative clock cycles, even when there are no write requests. The slots are fixed and they
are served in their respective slots only.
Round-Robin
Equal priority is given to read and write address channels in this mode. The grant to the
read and write channels depends on the last served request granted from the AXI master.
For example, if the last performed operation is write, then it gives precedence for read
operation to be served over write operation. Similarly, if the last performed operation is
read, then it gives precedence for write operation to be served over read operation. If both
read and write channels requests at the same time when there are no pending requests, this
scheme serves write channel ahead of read.
Read Priority (RD_PRI_REG)
Read and write address channels are served with equal priority in this mode. The requests
from the write address channel are processed when one of the following occurs:
• No pending requests from read address channel.
• Read starve limit of 256 is reached. It is only checked at the end of the burst.
• Read wait limit of 16 is reached.
• Write QOS is higher which is non-zero. It is only checked at the end of the burst.
The requests from the read address channel are processed in a similar method.
Read Priority with Starve Limit (RD_PRI_REG_STARVE_LIMIT)
The read address channel is always given priority in this mode. The requests from the write
address channel are processed when there are no pending requests from the read address
channel or the starve limit for read is reached.
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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