Xilinx Zynq-7000 User Manual page 506

Read Stage 1 Calibration Debug Signals
Table 3-30 indicates the mapping between bits within the dbg_rd_stage1_cal bus and
debug signals in the PHY. All signals are found within the qdr_rld_phy_rdlvl module
and are all valid in the clk domain.
Table 3-30: Read Stage 1 Debug Signal Map
Bits
dbg_rd_stage1_cal[2:0]
dbg_rd_stage1_cal[7:6]
dbg_rd_stage1_cal[14:12]
dbg_rd_stage1_cal[15]
dbg_rd_stage1_cal[16]
dbg_rd_stage1_cal[17]
dbg_rd_stage1_cal[25:18]
dbg_rd_stage1_cal[31]
dbg_rd_stage1_cal[32]
dbg_rd_stage1_cal[48:41]
dbg_rd_stage1_cal[56:49]
dbg_rd_stage1_cal[57]
dbg_rd_stage1_cal[66:61]
dbg_rd_stage1_cal[72:67]
dbg_rd_stage1_cal[78:73]
dbg_rd_stage1_cal[81]
dbg_rd_stage1_cal[82]
dbg_rd_stage1_cal[85:83]
dbg_rd_stage1_cal[91]
dbg_rd_stage1_cal[96:92]
dbg_rd_stage1_cal[102:97]
dbg_rd_stage1_cal[108:103]
dbg_rd_stage1_cal[109]
dbg_rd_stage1_cal[154+:40]
dbg_rd_stage1_cal[194+:48]
dbg_rd_stage1_cal[194+:48]
dbg_rd_stage1_cal[194+:48]
dbg_rd_stage1_cal[378+:48]
dbg_rd_stage1_cal[426+:48]
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
PHY Signal Name
sm_r
seq_sm_r
rdlvl_work_lane_r
rdlvl_stg1_start
rdlvl_stg1_done
rdlvl_stg1_start
rdlvl_stg1_cal_bytes_r
cmplx_rdcal_start
cmplx_rd_data_valid
rd_data_comp_r
iserdes_comp_r
rdlvl_lane_match
largest_left_edge
smallest_right_edge
mem_out_dec
rdlvl_pi_stg2_f_incdec
rdlvl_pi_en_stg2_f
pi_lane_r
prev_match_r
match_out_r
samp_cnt_r
samps_match_r
samp_result_held_r
simp_dlyval_r
simp_left_r
simp_right_r
simp_center_r
cmplx_left_r
cmplx_right_r
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Description
Read level main state machine.
Read level sequence state bits.
Lane currently undergoing read level calibration.
Write side signal causing read level block to start.
Read level block signals completion.
Write side signal causing read level to copy first lane
result across all lanes.
Lanes for which write side is requesting calibration.
Write side signal causing read level to do complex cal.
Write side signal informing read level that complex read
data is valid.
Per byte comparison results for complex calibration.
Per byte comparison results for simple calibration.
Overall comparison result for both simple and complex.
Phaser in taps when the right most left edge was found.
Phaser in taps when the left most right edge was found.
Output of static compensation ROM.
Controls directing of phaser in stepping.
Phaser in step command.
Lane to which phaser in commands apply.
Previous sample matched.
idelay of last detected invalid to valid match transition.
Sample counter.
Cumulative sample match count.
Result from previous sample cycle.
Five bits per lane dlyval results for simple pattern.
Six bits per lane left results for simple pattern.
Six bits per lane right results for simple pattern.
Six bits per lane center results for simple pattern.
Six bits per lane left results for complex pattern.
Six bits per lane right results for complex pattern.
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