Xilinx Zynq-7000 User Manual page 341

Table 2-13: QDR II+ SRAM Memory Interface Solution Pinout Parameters (Cont'd)
Parameter
CQ_MAP
ADD_MAP
RD_MAP
WR_MAP
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Description
Bank and byte lane position
information for the read clocks
(CQ/CQ#). See the K_MAP
description. This parameter varies
based on the pinout and should
not be changed manually in
generated design.
Bank and byte lane position
information for the address. 12-bit
parameter provided per pin.
• [11:8] – Bank position. Values of
0, 1, or 2 are supported.
• [7:4] – Byte lane position within a
bank. Values of 0, 1, 2, or 3 are
supported.
• [3:0] – Bit position within a byte
lane. Values of [0, 1, 2, . . ., A, B]
are supported.
This parameter varies based on the
pinout and should not be changed
manually in generated design.
Bank and byte lane position
information for the Read enable.
See the ADD_MAP description. This
parameter varies based on the
pinout and should not be changed
manually in generated design.
Bank and byte lane position
information for the Write enable.
See the ADD_MAP description. This
parameter varies based on the
pinout and should not be changed
manually in generated design.
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Chapter 2: QDR II+ Memory Interface Solution
Example
See the K_MAP example.
Upper-most Data Write/Data Read or
Address/Control byte group. The selected bank is
referred to as Bank 0 in the parameters notation.
Numbering of banks is 0, 1, and 2 from top to
bottom.
Byte groups T0, T1, T2, and T3 are numbered in
parameters as 3, 2, 1, and 0, respectively.
Bottom-most pin in a byte group is referred as '0'
in MAP parameters.
Bottom-most pin in a byte group is referred as '0'
in the MAP parameters. Numbering is counted
from 0 to 9 from the bottom-most pin to the top
pin within a byte group by excluding DQS I/Os.
DQS_N and DQS_P pins of a byte group are
numbered as A and B, respectively.
264'h000_000_239_238_237_236_23B_23A_235_2
34_233_232_231_230_229_228_227_226_22B_22
A_225_224: This parameter is denoted for an
Address width of 22 bits with 12 bits for each pin.
In this example, the Address width is 20 bits.
Ordering of parameters is from MSB to LSB (that
is, SA[0] corresponds to the 12 LSBs of the
parameter).
12'h224: Address pin placed in bank 2, byte lane
2, at location 4.
12'h11A: Address pin placed in bank 1, byte lane
1, at location A.
See the ADD_MAP example.
See the ADD_MAP example.
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