Xilinx Zynq-7000 User Manual page 504

Table 3-28: DEBUG_PORT Signal Descriptions (Cont'd)
Signal
dbg_po_f_dec
dbg_pi_tap_cnt[5:0]
dbg_po_tap_cnt[5:0]
dbg_rd_stage1_rtr_error[N_DATA_LANES – 1:0]
dbg_rd_stage1_error[N_DATA_LANES – 1:0]
dbg_cq_num[CQ_BITS – 1:0]
dbg_valid_lat[4:0]
dbg_idel_tap_cnt_sel[TAP_BITS – 1:0]
dbg_inc_latency
dbg_error_max_latency
dbg_error_adj_latency
dbg_rd_data_rd[nCK_PER_CLK × 9 – 1:0]
dbg_rd_data_fd[nCK_PER_CLK × 9 – 1:0]
dbg_rd_valid
dbg_wrcal_sel_stg[1:0]
dbg_wrcal[63:0]
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Direction Description
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output
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This signal increments the PHASER_OUT
generated OSERDES clk that is used to
capture falling data.
This output indicates the current
PHASER_IN tap count position.
This output indicates the current
PHASER_OUT tap count position.
(RLDRAM 3 only) Per byte lane error
signal indicating valid window not found
during read training register stage 1 read
calibration.
Per byte lane error signal indicating valid
window not found during stage 1 read
calibration.
This signal indicates the current byte
lane selected (either during calibration
or through the debug port).
Latency in cycles of the delayed read
command.
Current IDELAY tap setting for bits
selected using dbg_bit_sel.
This output indicates that the latency of
the corresponding byte lane was
increased to ensure proper alignment of
the read data to the user interface.
This signal indicates that the latency
could not be measured before the
counter overflowed. Each device has one
error bit.
This signal indicates that the target
PHY_LATENCY could not be achieved.
This bus shows the captured output of
the rising data for a single byte lane,
selected using dbg_byte_sel.
This bus shows the captured output of
the falling data for a single byte lane,
selected using dbg_byte_sel.
Read data valid signal that aligns with
the dbg_rd_data_rd and dbg_rd_data_fd.
Selects which stage of write calibration
to output: dbg_wrcal_po_first_edge,
dbg_wrcal_po_second_edge, or
dbg_wrcal_po_final.
General Debug port for write calibration
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